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Học thiết kế mạch bằng VHDL và Verilog thông qua ví dụ #1

Bảng 5‑1 và Bảng 5‑2 miêu tả mạch trong Hình 5‑1 lần lượt bằng Verilog và VHDL.

VHDL vs. Verilog

Hình 5‑1. Sơ đồ mạch ví dụ 1

Bảng 5‑1. Miêu tả bằng Verilog cho mạch ví dụ 1

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 Module home_alarm (a,s,m);

Input [3:0] s;

Input m;

Output a;

Assign a = (s[0]| s[1]| s[2]| s[3]) & m;

endmodule

Bảng 5‑2.  Miêu tả bằng VHDL cho mạch ví dụ 1

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 Library ieee;

Use ieee.std_logic_1164.all;

Entity home_Alarm is

 Port (s: in std_logic_vector (3 downto 0);

         M: in std_logic;

         A: out std_logic);

End home_alarm;

Architecture dataflow_model of home_alarm is

Begin

  A <= (s(0) or s(1) or s(2) or s(3)) and m

End dataflow_model;

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Nguyễn Kiêm Hùng

Hung K. Nguyen studied “Electronic Engineering” in both his bachelor’s and master’s degrees at the Vietnam National University, Hanoi, Vietnam. He received the bachelor’s degree in 2003. After receiving his bachelor’s degree, He worked as an internship in the Research Center of Electronics and Telecommunications. In 2006, He received the master’s degree in electronic engineering from VNU University of Engineering and Technology (VNU-UET). Before pursuing his Ph.D’s degree, He worked as a researcher at the Laboratory for Smart Integrated Systems in VNU University of Engineering and Technology for two years. In 2008, He went to Southeast University, Nanjing, China to get his Ph.D degree. He received the Ph.D. degree in Microelectronics and Solid State Electronics from Southeast University in 2013. After got his Ph.D’s degree, He returned to VNU University of Engineering and Technology to continue his research in VLSI design. He works currently as an assistant professor and senior researcher at VNU Key Laboratory for Smart Integrated Systems. His research interests mainly include multimedia processing, reconfigurable computing, and SoC designs.

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